A 1-GS/s 11-b Time-Interleaved SAR ADC With Robust, Fast, and Accurate Autocorrelation-Based Background Timing-Skew Calibration

被引:2
作者
Gu, Mingyang [1 ]
Tao, Yunsong [1 ]
He, Xiyu [1 ]
Zhong, Yi [1 ]
Jie, Lu [2 ]
Sun, Nan [1 ]
机构
[1] Tsinghua Univ, Dept Elect Engn, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Sch Integrated Circuits, Beijing 100084, Peoples R China
关键词
Calibration; Clocks; Bandwidth; Autocorrelation; Convergence; Accuracy; Voltage; Analog-to-digital converter (ADC); autocorrelation-based timing-skew calibration; background calibration; clock booster; time-interleaved (TI) ADC; 6-BIT; 10-B;
D O I
10.1109/JSSC.2024.3421363
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work proposes an autocorrelation-based background timing-skew calibration method. It uses the correlations between adjacent channels to extract timing-skew errors, which relaxes the input bandwidth limitation up to the Nyquist frequency. Moreover, the proposed technique simultaneously detects all channels' timing-skew errors, guaranteeing fast and accurate convergence. This work also proposes a clock booster. It has a simple structure and can efficiently increase the voltage swing of the clock signal. Equipped with the proposed techniques, a 1-GS/s 11-bit four-channel time-interleaved (TI) SAR analog-to-digital converter (ADC) achieves 59.3-dB SNDR and 78.8-dB SFDR with all skew tones below - 80 dB at the Nyquist input. The total power dissipation is only 3.7 mW with digital computations implemented off-chip. This corresponds to the Schreier FoM of 170.6 dB and Walden FoM of 4.9 fJ/conv-step.
引用
收藏
页码:421 / 431
页数:11
相关论文
共 31 条
  • [11] Guo MQ, 2019, SYMP VLSI CIRCUITS, pC76, DOI [10.23919/vlsic.2019.8778077, 10.23919/VLSIC.2019.8778077]
  • [12] A 1.6-GS/s 12.2-mW Seven-/Eight-Way Split Time-Interleaved SAR ADC Achieving 54.2-dB SNDR With Digital Background Timing Mismatch Calibration
    Guo, Mingqiang
    Mao, Jiaji
    Sin, Sai-Weng
    Wei, Hegong
    Martins, Rui P.
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55 (03) : 693 - 705
  • [13] A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques
    Huang, Chun-Cheng
    Wang, Chung-Yi
    Wu, Jieh-Tsorng
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2011, 46 (04) : 848 - 858
  • [14] A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration
    Jamal, SM
    Fu, DH
    Chang, NCJ
    Hurst, PJ
    Lewis, SH
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (12) : 1618 - 1627
  • [15] A Time-Interleaved 12-b 270-MS/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme
    Kang, Hyun-Wook
    Hong, Hyeok-Ki
    Kim, Wan
    Ryu, Seung-Tak
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (09) : 2584 - 2594
  • [16] Le Dortz N, 2014, ISSCC DIG TECH PAP I, V57, P386, DOI 10.1109/ISSCC.2014.6757481
  • [17] A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration
    Lee, Sunghyuk
    Chandrakasan, Anantha P.
    Lee, Hae-Seung
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2014, 49 (12) : 2846 - 2856
  • [18] A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs
    Li, Jing
    Wu, Shuangyi
    Liu, Yang
    Ning, Ning
    Yu, Qi
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2014, 61 (07) : 486 - 490
  • [19] A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique
    Lin, Chin-Yu
    Wei, Yen-Hsin
    Lee, Tai-Cheng
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2018, 53 (05) : 1508 - 1517
  • [20] A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure
    Liu, Chun-Cheng
    Chang, Soon-Jyh
    Huang, Guan-Ying
    Lin, Ying-Zu
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2010, 45 (04) : 731 - 740