A Scalable and PVT Invariant Spiking Neuron Using Asynchronous CMOS Logic

This paper introduces a unique asynchronous digital version of the widely recognized LIF neuron model, which is commonly used in spiking neural networks. This proposed circuit provides a technologically scalable alternative to conventional analog implementations. Despite utilizing digital logic, the neuron circuit employs internal variable representations that are rate encoded as spike trains. This approach simplifies the internal circuitry by eliminating the need for arithmetic circuits and minimizes power consumption, achieving a figure of merit of 310 fJ/SOP. The programmability of the parameters, combined with these features, facilitates the use of off-chip gradient learning techniques without performance degradation due to PVT and mismatch variations during deployment.