Real-Time SSVEP Measurements Through Lock-In Detection in FPGA-Based Platform

被引:0
作者
Oliva, Matias [1 ]
Guerrero, Federico [1 ]
Garcia, Pablo [1 ]
Spinelli, Enrique [1 ]
机构
[1] Univ Nacl La Plata, Inst LEICI UNLP CONICET CIC, Fac Ingn, 116 & 48, RA-1900 La Plata, Argentina
来源
ADVANCES IN BIOENGINEERING AND CLINICAL ENGINEERING, VOL 1, SABI 2023 | 2024年 / 106卷
关键词
SSVEP; FPGA; EEG; Lock-in; FREQUENCY; AMPLIFIER;
D O I
10.1007/978-3-031-61960-1_16
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
In this work, a method for measuring steady-state visually evoked potentials using the Lock-In technique is presented. The proposed method involves acquiring the electroencephalography signal through channel averaging from an ADS1299 sigma-delta converter, without the need for additional hardware to accommodate the signal and processing in real-time using an IntelMAX10 FPGA, while visual stimuli synchronizedwith the sampling and processing are generated. The result is a robust platform that allows determining a user's attention focus on visual stimuli flickering at 14.70, 16.67, and 19.23 Hz. The initial experimental tests of the system with three subjects validated the platform, obtaining an average signal-to-noise ratio of 3.2 in the detection, with a maximum of 6.2 in the case of an experienced SSVEP user.
引用
收藏
页码:161 / 171
页数:11
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