Silicon cross-coupled gated tunneling diodes

被引:1
|
作者
Tang, Zhenyun [1 ,2 ]
Wang, Zhe [2 ,3 ]
Song, Zhigang [1 ,2 ]
Zheng, Wanhua [1 ,2 ]
机构
[1] Chinese Acad Sci, Inst Semicond, Lab Solid State Optoelect Informat Technol, Beijing 100083, Peoples R China
[2] Univ Chinese Acad Sci, Beijing 100049, Peoples R China
[3] Chinese Acad Sci, Inst Semicond, State Key Lab Superlatt & Microstruct, Beijing 100083, Peoples R China
来源
CHIP | 2024年 / 3卷 / 02期
关键词
Low power; Silicon-based tunneling device; Negative differential resistance (NDR); Peak-to-valley current ratio (PVCR); TCAD simulation; SRAM BIT CELL; LOW LEAKAGE; DESIGN; SI;
D O I
10.1016/j.chip.2024.100094
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Tunneling-based static random-access memory (SRAM) devices have been developed to ful fi ll the demands of high density and low power, and the performance of SRAMs has also been greatly promoted. However, for a long time, there has not been a silicon based tunneling device with both high peak valley current ratio (PVCR) and practicality, which remains a gap to be fi lled. Based on the existing work, the current manuscript proposed the concept of a new silicon-based tunneling device, i.e., the silicon crosscoupled gated tunneling diode (Si XTD), which is quite simple in structure and almost completely compatible with mainstream technology. With technology computer aided design (TCAD) simulations, it has been validated that this type of device not only exhibits signi fi cant negative-differential-resistance (NDR) behavior with PVCRs up to 10 6 , but also possesses reasonable process margins. Moreover, SPICE simulation showed the great potential of such devices to achieve ultralow-power tunneling-based SRAMs with standby power down to 10 - 12 W.
引用
收藏
页数:9
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