Exploring the Landscape of Phase-Locked Loop Architectures: A Comprehensive Review

被引：8

作者：

Dutta, Debojyoti ^{[1
]}

Pranshu Tumukunta, Sai ^{[1
]}

Sivaraaj, N. R. ^{[1
]}

Abdul Majeed, K. K. ^{[1
]}

机构：

[1] Vellore Inst Technol VIT, Sch Elect Engn, Vellore 632014, Tamil Nadu, India

来源：

IEEE ACCESS | 2024年 / 12卷

关键词：

Phase locked loops; Voltage-controlled oscillators; Voltage control; Phase noise; Charge pumps; Transfer functions; Taxonomy; ADPLL; Basic Phase Locked Loop (PLL); CPPLL; Dual PLL; Digital PLL; Enhanced PLL; FOM; Integer PLL; LCVCO PLL; Lock time; LPPLL; Operating frequency; Phase Noise; SSPLL; FREQUENCY DETECTOR; LOW-JITTER; PLL ARCHITECTURE; FAST-LOCKING; DESIGN; CMOS; SYSTEM; IMPLEMENTATION; SYNTHESIZER; BANDWIDTH;

D O I：

10.1109/ACCESS.2024.3446393

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper aims to explore diverse landscape of Phase Locked Loops (PLLs), offering a comprehensive categorization and in-depth analysis of their underlying working principles. Addressing the challenges of differentiation within this complex field, the review meticulously examines a curated selection of prominent research papers and articles encompassing a diverse range of PLL types. The taxonomy, meticulously constructed based on architectural and functional criteria, classifies various PLL categories precisely, elucidating the modifications implemented for optimal performance. To further enhance comprehension, a detailed block diagram architecture of a typical PLL system is presented alongside a comprehensive table showcasing operational parameters across different categories. The review presents illustrative graphs of various operational parameters, which include Power Consumption, Phase Noise, Output Frequency, Area, Figure of Merit(FOM), and lock time, enabling the visualization of trends over time. This work provides a significant contribution thereby assisting the budding researchers with insights and comparisons.

引用

页码：125523 / 125543

页数：21

共 154 条

[1] Efficient and flexible simulation of phase locked loops, Part I: Simulator design [J].

Abramovitch, Daniel Y. .

2008 AMERICAN CONTROL CONFERENCE, VOLS 1-12, 2008, :4672-4677

[2] Memristor-Based Loop Filter Design for Phase Locked Loop [J].

Adesina, Naheem Olakunle ;

Srivastava, Ashok .

JOURNAL OF LOW POWER ELECTRONICS AND APPLICATIONS, 2019, 9 (03)

[3] Demodulation type single-phase PLL with DC offset rejection [J].

Ahmed, H. ;

Benbouzid, M. .

ELECTRONICS LETTERS, 2020, 56 (07) :344-346

[4]

Al-araji S. R., 2006, Digital Phase Lock Loops, DOI [10.1007/978-0-387-32864-5_1, DOI 10.1007/978-0-387-32864-5_1]

[5]

Althoff M, 2011, ICCAD-IEEE ACM INT, P659, DOI 10.1109/ICCAD.2011.6105400

[6] Analysis and Design Techniques for Supply-Noise Mitigation in Phase-Locked Loops [J].

Arakali, Abhijith ;

Gondi, Srikanth ;

Hanumolu, Pavan Kumar .

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2010, 57 (11) :2880-2889

[7] Low-Power Supply-Regulation Techniques for Ring Oscillators in Phase-Locked Loops Using a Split-Tuned Architecture [J].

Arakali, Abhijith ;

Gondi, Srikanth ;

Hanumolu, Pavan Kumar .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2009, 44 (08) :2169-2181

[8] Phase shifter based on DDS-driven offset-PLL [J].

Avitabile, G. ;

Cannone, F. ;

Vania, A. .

ELECTRONICS LETTERS, 2006, 42 (25) :1438-1439

[9] Design & Implementation of High Speed and Low Power PLL Using GPDK 45 nm Technology [J].

Badiger N.A. ;

Iyer S. .

Journal of The Institution of Engineers (India): Series B, 2024, 105 (02) :239-249

[10] A CMOS implementation of controller based all digital phase locked loop (ADPLL) [J].

Balikai, Vikas ;

Kittur, Harish .

CIRCUIT WORLD, 2021, 47 (01) :71-85

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