Transition-Code Based Linearity Test Method for Pipelined ADCs With Digital Error Correction

被引：15

作者：

Lin, Jin-Fu ^{[1
]}

Chang, Soon-Jyh ^{[1
]}

Kung, Te-Chieh ^{[2
]}

Ting, Hsin-Wen ^{[3
]}

Huang, Chih-Hao ^{[4
]}

机构：

[1] Natl Cheng Kung Univ, Tainan 70101, Taiwan

[2] ALi Technol, Taipei 11493, Taiwan

[3] Natl Kaohsiung Univ Appl Sci, Kaohsiung 80778, Taiwan

[4] Himax Technol, Tainan 74148, Taiwan

来源：

IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2011年 / 19卷 / 12期

关键词：

Analog-to-digital converter (ADC); design-for-test (DfT); differential nonlinearity (DNL); integral nonlinearity (INL); pipelined; static linearity test; transition code;

D O I：

10.1109/TVLSI.2010.2089543

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A transition-code based method is proposed to reduce the linearity testing time of pipelined analog-to-digital converters (ADCs). By employing specific architecture-dependent rules, only a few specific transition codes need to be measured to accomplish the accurate linearity test of a pipelined ADC. In addition, a simple digital Design-for-Test (DfT) circuit is proposed to help correctly detect transition codes corresponding to each pipelined stage. With the help of the DfT circuit, the proposed method can be applied for pipelined ADCs with digital error correction (DEC). Experimental results of a practical chip show that the proposed method can achieve high test accuracy for a 12-bit 1.5-bit/stage pipelined ADC with different nonlinearities by measuring only 9.3% of the total measured samples of the conventional histogram based method.

引用

页码：2158 / 2169

页数：12

共 22 条

[1] On chip testing data converters using static parameters [J].