Analyses, Modeling, and SVPWM Control of a Three-Level T-NPC Inverter to Reduce Common-Mode Voltage Under Open-Circuit Fault in a Neutral-Point Switch

This paper proposes a new space vector pulse-width modulation technique for reducing the common-mode voltage (SVPWM2) in a three-level T-type neutral-point-clamped voltage source inverter working under switch-open-circuit fault on a neutral-point-connected switch. Under this circumstance, the space vector diagram of the inverter becomes asymmetrical so that if the conventional reduced common-mode voltage space vector PWM (SVPWM1) patterns are still applied to IGBT drivers, the output waveforms are heavily deformed, thus leading to deteriorated harmonic distortion. Regarding SOC fault tolerant control, there are several traditional methods available. However, they are either costly due to additional hardware expenses or suffer from poor PMW performances using only two voltage level (2L) switching techniques. To address these issues, this paper introduces a cost-effective strategy: a reduced CMV space vector PWM strategy for fault tolerant control. This approach utilizes a hybrid two- and three-level switching principle to enhance PWM performances, resulting in reduced output harmonic distortion, lower voltage stress, and lower switching loss compared to the economical 2L PWM method. The SVPWM2 algorithm is firstly analyzed and synthesized in the alpha - beta coordinates and then implemented in MATLAB/Simulink and experimental hardware with TMS320F28377 microcontroller. Simulation and experiment waveforms are further evaluated in terms of total harmonic distortion and weighted total harmonic distortion to validate the effectiveness of the proposed algorithm.