A Dithered-Digital-Mixing Background Timing-Skew Calibration Method for Time-Interleaved ADCs

被引:0
作者
Tao, Yunsong [1 ]
Zhong, Yi [1 ]
Shao, Jin [2 ]
Men, Changyou [3 ]
Jie, Lu [4 ]
Sun, Nan [1 ]
机构
[1] Tsinghua Univ, Dept Elect Engn, Beijing, Peoples R China
[2] Beijing Smartchip Microelect Technol Co Ltd, Beijing, Peoples R China
[3] Hangzhou Vango Technol Inc, Hangzhou, Peoples R China
[4] Tsinghua Univ, Sch Integrated Circuits, Beijing, Peoples R China
来源
2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年
关键词
time-interleaved; analog-to-digital converter; timing-skew; mismatch; background calibration; digital-mixing; dither;
D O I
10.1109/ISCAS58744.2024.10558642
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
This work proposes a dithered-digital-mixing background timing-skew calibration method for time-interleaved (TI) analog-to-digital converters (ADCs). Unlike prior digital-mixing methods that limit the input bandwidth or lead the calibration process to a limit cycle, the proposed method enhances the input bandwidth to the Nyquist frequency and guarantees the convergence. This is achieved by a pseudo-random binary sequence generator that produces a dither signal. Practical considerations including thermal noise and the step size of variable delay lines are discussed. Behavioral simulation results demonstrate the effectiveness of the proposed method with an improvement of signal-to-noise-and-distortion ratio from 26.3dB to 52.6dB for a 5GS/s 9b 16-channel TI ADC.
引用
收藏
页数:5
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