A Hardware Approach For Accelerating Inductive Learning In Description Logic

The employment of Machine Learning (ML) techniques in embedded systems has seen constant growth in recent years, especially for black-box ML techniques (such as Artificial Neural Networks (ANNs)). However, despite the successful employment of ML techniques in embedded environments, their performance potential is constrained by the limited computing resources of their embedded computers. Several hardware-based approaches were developed (e.g., using FPGAs and ASICs) to address the constraints of limited computing resources. The scope of this work focuses on improving the performance for Inductive Logic Programming (ILP) on embedded environments. ILP is a powerful logic-based ML technique that uses logic programming to construct human-interpretable ML models, where those logic-based ML models are capable of describing complex and multi-relational concepts. In this work, we present a hardware-based approach that accelerates the hypothesis evaluation task for ILPs in embedded environments that use Description Logic (DL) languages as their logic-based representation. In particular, we target the ALCQ((D)) language. According to experimental results (through an FPGA implementation), our presented approach has achieved speedups up to 48.7-fold for a disjunction of 32 concepts on 100 M individuals, where the baseline performance is the sequential CPU performance of the Raspberry Pi 4. For role and concrete role restrictions, the FPGA implementation achieved speedups up to 2.4-fold (for MIN cardinality role restriction on 1M role assertions); all FPGA implemented role and concrete role restrictions have achieved similar speedups. In the worst-case scenario, the FPGA implementation achieved either a similar or slightly better performance than the baseline (for all DL operations); the worst-case scenario resulted from using small datasets such as: using conjunction and disjunction on < 100 individuals, and using role and concrete (float/string) role restrictions on < 100,000 assertions.