Relationship between surface roughness and subsurface crack damage depth of sapphire crystals cut by diamond wire saw based on slicing experiments

Sapphire crystal with excellent properties is widely used as substrate materials for optoelectronics and microelectronics industries. Subsurface crack damage (SSD) will occur in the diamond wire saw slicing process of the sapphire wafer, which is related to the quality of the as-sawn wafer and the cost of subsequent processing. Therefore, rapid and effective detection of SSD is required in production. However, current detection methods are time-consuming and labor-intensive, thus requiring a fast, effective, and low-carbon evaluation method. In this paper, based on the current diamond wire saw slicing process parameters range of sapphire crystal in actual production, sawing experiments were carried out to study the surface and subsurface crack damage morphology characteristics, evolution law of surface roughness (Rz), and SSD. Furthermore, the mapping relationship between Rz and SSD was established by the numerical fitting method. The results show that, in the range of processing parameters for practical industrial applications, the surface of the as-sawn wafer was mainly formed by material brittleness removal, the subsurface presented a small number of micro-cracks and brittle fracture damage, and the median crack propagation direction was shifted. Within the range of process parameters used in this study, the maximum SSD value of the sapphire wafer is 20.07 mu m, the minimum value is 11.67 mu m, and the corresponding Rz values are 11.13 mu m and 8.12 mu m, respectively. Both SSD and Rz decreased with the increase in saw wire speed and the decrease in specimen feed speed. There is a nonlinear relationship of monotone increase between the two, which is SSD = 0.15Rz3 - 4.87Rz2 + 55.49Rz - 195.23. The research results can be used to evaluate SSD quickly and effectively by measuring as-sawn sapphire wafer Rz that can provide an experimental reference for wire-sliced SSD evaluation, wafer quality improvement, and processing parameter optimization.