Hardware Acceleration-Based Scheme for UNET Implementation Using FPGA

UNet has rapidly become the architecture of choice for precise real-time semantic segmentation, which is crucial in medical diagnostics and autonomous navigation applications. However, deploying such advanced Convolutional Neural Network (CNN) models on embedded devices is challenging due to UNet's computational complexity. This paper proposes an optimized FPGA-based hardware architecture to accelerate UNet for practical usage under power constraints without relying on GPUs. The proposed method utilizes processing elements for the convolutional process in sliding and multiplications. A shift register is employed to slide the window of the convolutional process, and a multiplier is used to multiply the input feature with the corresponding memory weight. The proposed method is implemented using VHDL and FPGA. The results show that the proposed method has a power consumption of 5.375 W with low latency, making it suitable for various domains.