A Universal Methodology of Complex Number Computation for Low-Complexity and High-Speed Implementation

被引:0
作者
Wang, Yu [1 ]
Zhang, Jin [2 ]
Wu, Youlong [2 ]
Lyu, Fei [3 ,4 ]
Luo, Yuanyong [5 ]
机构
[1] Nanjing Xiaozhuang Univ, Sch Elect Engn, Nanjing 211171, Peoples R China
[2] Jinling Inst Technol, Sch Elect & Informat Engn, Nanjing 211169, Peoples R China
[3] Nanjing Univ Aeronaut & Astronaut, Coll Integrated Circuits, Nanjing 211106, Peoples R China
[4] Nanjing Univ, Sch Phys, Nanjing 210093, Peoples R China
[5] Huawei Corp, Dept Turing Architecture Design, Linx Lab, HiSilicon, Shenzhen 518129, Peoples R China
基金
中国国家自然科学基金;
关键词
Hardware; Image segmentation; Software; Neural networks; Costs; Signal processing algorithms; Power demand; Optimization; Merging; Encoding; Piecewise linear (PWL) approximation method; computation for complex numbers; step-by-step truncation; square root calculation of complex numbers; reciprocal calculation of complex numbers; logarithm calculation of complex numbers; SQUARE-ROOT; ARCHITECTURE; DESIGN;
D O I
10.1109/TCSI.2024.3462806
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In complex-valued neural network (CVNN) applications, complex number calculations require high performance rather than high precision. However, most previous studies focused on high-precision approaches, which have low speed and high hardware costs. This paper proposes a universal methodology of complex number computation for low-complexity and high-speed implementation. The proposed methodology is based on the piecewise linear (PWL) method and can be used for different types of complex number computations. Considering that multiplication operations consume considerable resources, multiplication, fused square-add (FSA) and fused multiply-add (FMA) operations are the focus of optimization. The partial products of the square operation are reduced by folding and merging techniques because of their symmetry in the FSA operation. The partial products of the multiplication and FMA operations are reduced via Booth encoding. In addition, the partial products are further reduced by the proposed step-by-step truncation method. The proposed segmenter, which simulates the hardware implementation, automatically divides the nonlinear functions in the complex number computations into the smallest number of segments according to the required precision. The results show that the proposed approach improves performance and reduces hardware costs compared with the state-of-the-art methods for complex number calculations involving square roots, reciprocals and logarithms.
引用
收藏
页码:1308 / 1320
页数:13
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