An energy-efficient fi cient 32-bit bit-parallel superconducting SFQ specialized processor

As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy- efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32- bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.