Design and Implementation of Memory Management Unit for LoongArch Architecture

被引：0

作者：

Chen, Lin ^{[1
]}

Ma, Xiao ^{[1
]}

机构：

[1] Beijing Language & Culture Univ, Sch Informat Sci, Beijing 100000, Peoples R China

来源：

PROCEEDINGS OF 2023 7TH INTERNATIONAL CONFERENCE ON ELECTRONIC INFORMATION TECHNOLOGY AND COMPUTER ENGINEERING, EITCE 2023 | 2023年

基金：

中国国家自然科学基金;

关键词：

MMU; LoongArch; FPGA; CPU;

D O I：

10.1145/3650400.3650643

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A memory management unit (MMU) is designed and implemented for a 32-bit LoongArch architecture pipeline CPU using the FPAG platform. A simple yet performance-oriented TLB module is designed and implemented. TLB-related instructions from the LoongArch instruction set are added to the pipeline CPU. The virtual-to-physical address translation function of the MMU is achieved. Finally, the handling of MMU-related exceptions required by LoongArch32 is implemented. After software simulation and board testing, this solution meets the design requirements and can complete all the designed functions.

引用

页码：1447 / 1452

页数：6

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