Super-K: A Superscalar CRYSTALS-KYBER Processor Based on Efficient Arithmetic Array

被引:1
作者
Zhang, Jiaming [1 ]
Lu, Jiahao [1 ]
Li, Aobo [1 ]
Wang, Mingbo [1 ]
Li, Xiang [1 ]
Huang, Tianze [1 ]
Chen, Lei [1 ]
Liu, Dongsheng [1 ]
机构
[1] Huazhong Univ Sci & Technol, Sch Integrated Circuit, Wuhan 430074, Peoples R China
基金
中国国家自然科学基金;
关键词
Hardware; Computer architecture; Pipeline processing; Arithmetic; Quantum computing; Pulse width modulation; Micromechanical devices; CRYSTALS-KYBER; PQC; superscalar processor; AT product efficiency;
D O I
10.1109/TCSII.2024.3382772
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Security systems based on traditional cryptography mechanisms are at risk of being cracked by quantum computers in the future. CRYSTALS-KYBER (Kyber) as the NIST finalized lattice-based post-quantum cryptography (PQC) algorithm, will be widely used in public-key encryption scenarios. Although quantum-difficulty assumptions based on lattice math problems make Kyber quantum-resistant, how to effectively implement it into systems with different security needs remains a challenge. This brief presents a dual-issue superscalar Kyber processor (Super-K) that supports customized RISC-V instruction-set architecture (ISA) and implements the key encapsulation mechanism (KEM) flexibly and efficiently. A reconfigurable polynomial arithmetic unit (PAU) is designed, which optimizes the compress/decompress process, and accelerates polynomial operations efficiently by optimal parallelism. The pipelining scheduling technique is used in Super-K to improve instruction level parallelism and reduce time consumption. Super-K is implemented on UltraScale+ FPGA platform and evaluated under SMIC 40nm technology, which achieves the fastest computational speed with the lowest power consumption and $1.4\times /8.2\times $ improvement in FPGA/ASIC AT product efficiency.
引用
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页码:4286 / 4290
页数:5
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