Efficient HW/SW Co-design of FPGA Accelerator to Detect Anomaly Attacks in Smart Grids

The false data injection attack (FDIA) is emerging as a significant threat to the state estimation of smart grids. Approaches of FDIA detection based on deep learning have been proven to accurately identify the location of external attacks. However, these AI-based models require a large number of calculations, leading to excessive time and energy consumption. In order to tackle the challenges related to latency and energy efficiency in FDIA detection, this paper introduces a FPGA-based hardware-software co-design accelerator. In comparison to software implementations, our hardware accelerator significantly reduces inference latency and energy consumption without compromising detection accuracy. The proposed accelerator achieves up to 40x speedup compared to the ARM Cortex-A53 quad-core CPU, while consuming only a quarter of the CPU energy.