共 24 条
[2]
[Anonymous], 2018, SynopsysSentaurus Device User Guide
[3]
Cai Linlin, 2018, IEEE INT ELECT DEVIC
[4]
Chauhan Y.S., 2015, FINFET MODELING IC S
[5]
Interface-Trap Modeling for Silicon-Nanowire MOSFETs
[J].
2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM,
2010,
:977-980
[9]
Characterization and Analysis of Gate-All-Around Si Nanowire Transistors for Extreme Scaling
[J].
2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC),
2011,
[10]
Si nanowire FET and its modeling
[J].
SCIENCE CHINA-INFORMATION SCIENCES,
2011, 54 (05)
:1004-1011