Compact modeling of quantum confinements in nanoscale gate-all-around MOSFETs

被引:6
作者
Peng, Baokang [1 ]
Jiao, Yanxin [1 ]
Zhong, Haotian [1 ]
Rong, Zhao [1 ]
Wang, Zirui [2 ]
Xiao, Ying [3 ]
Wong, Waisum [1 ]
Zhang, Lining [1 ]
Wang, Runsheng [2 ]
Huang, Ru [2 ]
机构
[1] Peking Univ, Sch Elect & Comp Engn, Shenzhen 518055, Peoples R China
[2] Peking Univ, Sch Integrated Circuits, Beijing 100871, Peoples R China
[3] Hisilicon Corp, Shanghai 201700, Peoples R China
来源
FUNDAMENTAL RESEARCH | 2024年 / 4卷 / 05期
关键词
Gate-all-around FET; Compact model; Quantum mechanical confinement; Nanosheet FET; Nanowire FET; Sub-band energy; NANOWIRE; SI;
D O I
10.1016/j.fmre.2022.09.035
中图分类号
O [数理科学和化学]; P [天文学、地球科学]; Q [生物科学]; N [自然科学总论];
学科分类号
07 ; 0710 ; 09 ;
摘要
In this work, a surface-potential based compact model focusing on the quantum confinement effects of ultimately scaled gate-all-around (GAA) MOSFET is presented. Energy quantization with sub-band formation along the radius direction of cylindrical GAAs or thickness direction of nanosheet GAAs leads to significant quantization effects. An analytical model of surface potentials is developed by solving the Poisson equation with incorporating sub- band effects. In combination with the existing transport model framework, charge-voltage and current-voltage formulations are developed based on the surface potential. The model formulations are then extensively validated using TCAD numerical simulations as well as Si data of nanosheet GAA MOSFETs. Simulations of typical circuits verify the model robustness and convergence for its applications in GAA technology.
引用
收藏
页码:1306 / 1313
页数:8
相关论文
共 24 条
[1]   Analytical Monolayer MoS2 MOSFET Modeling Verified by First Principle Simulations [J].
Ahmed, Zubair ;
Shi, Qing ;
Ma, Zichao ;
Zhang, Lining ;
Guo, Hong ;
Chan, Mansun .
IEEE ELECTRON DEVICE LETTERS, 2020, 41 (01) :171-174
[2]  
[Anonymous], 2018, SynopsysSentaurus Device User Guide
[3]  
Cai Linlin, 2018, IEEE INT ELECT DEVIC
[4]  
Chauhan Y.S., 2015, FINFET MODELING IC S
[5]   Interface-Trap Modeling for Silicon-Nanowire MOSFETs [J].
Chen, Zuhui ;
Zhou, Xing ;
Zhu, Guojun ;
Lin, Shihuan .
2010 INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM, 2010, :977-980
[6]   BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs [J].
Dasgupta, Avirup ;
Parihar, Shivendra Singh ;
Kushwaha, Pragya ;
Agarwal, Harshit ;
Kao, Ming-Yen ;
Salahuddin, Sayeef ;
Chauhan, Yogesh Singh ;
Hu, Chenming .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2020, 67 (02) :730-737
[7]   Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition [J].
Dasgupta, Avirup ;
Rastogi, Priyank ;
Agarwal, Amit ;
Hu, Chenming ;
Chauhan, Yogesh Singh .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2018, 65 (03) :1094-1100
[8]   Unified Compact Model for Nanowire Transistors Including Quantum Effects and Quasi-Ballistic Transport [J].
Dasgupta, Avirup ;
Agarwal, Amit ;
Chauhan, Yogesh Singh .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2017, 64 (04) :1837-1845
[9]   Characterization and Analysis of Gate-All-Around Si Nanowire Transistors for Extreme Scaling [J].
Huang, Ru ;
Wang, Runsheng ;
Zhuge, Jing ;
Liu, Changze ;
Yu, Tao ;
Zhang, Liangliang ;
Huang, Xin ;
Ai, Yujie ;
Zou, Jinbin ;
Liu, Yuchao ;
Fan, Jiewen ;
Liao, Huailin ;
Wang, Yangyuan .
2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC), 2011,
[10]   Si nanowire FET and its modeling [J].
Iwai, Hiroshi ;
Natori, Kenji ;
Shiraishi, Kenji ;
Iwata, Jun-ichi ;
Oshiyama, Atsushi ;
Yamada, Keisaku ;
Ohmori, Kenji ;
Kakushima, Kuniyuki ;
Ahmet, Parhat .
SCIENCE CHINA-INFORMATION SCIENCES, 2011, 54 (05) :1004-1011