Equalization for Compensation of Intersymbol Relationship of Multi-Valued Signaling Using Two-Dimensional Symbol Mapping

被引:0
作者
Iijima, Yosuke [1 ]
Okada, Atsunori [1 ]
Yuminaka, Yasushi [2 ]
机构
[1] Natl Inst Technol, KOSEN, Oyama Coll, Oyama, Japan
[2] Gunma Univ, Grad Sch Sci & Technol, Kiryu, Gumma, Japan
来源
2024 IEEE 54TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, ISMVL 2024 | 2024年
关键词
Multi-valued signaling; Inter-symbol interference; Feed forward equalizer; Two-dimensional symbol mapping; Linear mixture model;
D O I
10.1109/ISMVL60454.2024.00014
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
This paper introduces a novel equalization scheme for multi-valued data transmission based on inter-symbol relationships using a two-dimensional (2D) symbol map. In highspeed data transmission, the transmission line acts as a low-pass filter and contributes to inter-symbol interference (ISI) at the receiver. The ISI effect, in turn, hinders the realization of high-speed serial-link systems. To mitigate this ISI effect at the receiver, a transmit feed forward equalizer (FFE), mimicking a high-pass filter, is applied to compensate for the transmission characteristics. This study proposes an innovative equalization scheme that focuses on the compensation of inter-symbol relationships in two-dimensional symbol maps for multi-valued signaling. By employing a transmit FFE with low-pass characteristics, the proposed equalizer controls the symbol distribution on a 2D symbol map, leading to the convergence of the variation in symbol distribution. Simulations demonstrate that this low-pass FFE can effectively suppress the surge in high-frequency signals within the transmitted signal, thereby diminishing the ISI impact at the receiver by controlling the symbol distribution on the 2D symbol map. This result underscores the potential of this novel equalization scheme for advancing high-speed multi-valued data transmission systems.
引用
收藏
页码:19 / 24
页数:6
相关论文
共 9 条
[1]  
Barry J.R., 2004, DIGITAL COMMUNICATIO
[2]   Effect of Equalization Bandwidth and Linearity on NRZ and PAM4 Eye Diagram [J].
Delshadpour, Siamak ;
Yan, Peng .
2022 29TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (IEEE ICECS 2022), 2022,
[3]   Equalization Enhancement Approaches for PAM4 Signaling for Next Generation Speeds [J].
He, J. ;
Dikhaminjia, N. ;
Tsiklauri, M. ;
Drewniak, J. ;
Chada, A. ;
Mutnury, B. .
2017 IEEE 67TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2017), 2017, :1874-1879
[4]  
Iijima Yosuke, 2023, 2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL), P99, DOI 10.1109/ISMVL57333.2023.00029
[5]   A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET [J].
Kim, Jihwan ;
Kundu, Sandipan ;
Balankutty, Ajay ;
Beach, Matthew ;
Kim, Bong Chan ;
Kim, Stephen T. ;
Liu, Yutao ;
Murthy, Savyasaachi Keshava ;
Wali, Priya ;
Yu, Kai ;
Kim, Hyung Seok ;
Liu, Chuan-Chang ;
Shin, Dongseok ;
Cohen, Ariel ;
Segal, Yoav ;
Fan, Yongping ;
Li, Peng ;
O'Mahony, Frank .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2022, 57 (01) :6-20
[6]   A 10-Gb/s Eye-Opening Monitor Circuit for Receiver Equalizer Adaptations in 65-nm CMOS [J].
Lin, Yu-Chuan ;
Tsao, Hen-Wai .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2020, 28 (01) :23-34
[7]   A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS [J].
Toprak-Deniz, Zeynep ;
Proesel, Jonathan E. ;
Bulzacchelli, John F. ;
Ainspan, Herschel A. ;
Dickson, Timothy O. ;
Beakes, Michael P. ;
Meghelli, Mounir .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2020, 55 (01) :19-26
[8]   A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor [J].
Won, Hyosup ;
Lee, Joon-Yeong ;
Yoon, Taehun ;
Han, Kwangseok ;
Lee, Sangeun ;
Park, Jinho ;
Bae, Hyeon-min .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2017, 64 (03) :664-674
[9]  
Yuminaka Yasushi, 2023, 2023 IEEE 53rd International Symposium on Multiple-Valued Logic (ISMVL), P94, DOI 10.1109/ISMVL57333.2023.00028