Design of time-sensitive network switch based on FPGA

Time-sensitive network defines the time-sensitive mechanism of Ethernet data transmission, which increases the real-time, determinacy and reliability for Ethernet, and can provide real-time and reliable services for the transmission of key data, thus becoming a new generation of deterministic network solutions with great competitiveness. Network switch is the core of system-level deterministic transmission in time-sensitive networks, and FPGA with reconfigurable function is the first choice for TSN switch design and implementation. A time-sensitive network switch is designed based on FPGA, which provides 16 Gigabit Ethernet interfaces and supports shaping and scheduling functions such as IEEE802.1Qav and IEEE802.1Qbv. RFC2544performance test results show that all seven typical byte packets can be forwarded at 100% line speed with a packet loss rate of 0.