Analytical Modeling of Short-Channel MOSFET Differential Pair Non-Linearity

被引:1
|
作者
Pekcokguler, Naci [1 ,2 ,3 ]
Han, Hung-Chi [4 ]
Morche, Dominique [3 ]
Dehollain, Catherine [4 ,5 ]
Burg, Andreas [5 ]
Enz, Christian
机构
[1] MINATEC Campus, CEA, LETI, F-38054 Grenoble, France
[2] Ecole Polytech Fed Lausanne, CH-1015 Lausanne, Switzerland
[3] Analog Devices Inc, D-85737 Munich, Germany
[4] Ecole Polytech Fed Lausanne EPFL, CH-2000 Neuchatel, Switzerland
[5] Ecole Polytech Fed Lausanne EPFL, CH-1015 Lausanne, Switzerland
关键词
Integrated circuit modeling; Semiconductor device modeling; Analytical models; MOSFET; Circuits; Transistors; Power demand; MOSFET non-linearity model; differential pair non-linearity; charge-based; EKV model; drain voltage induced non-linearity; OTA non-linearity; amplifier non-linearity; CMOS; OPTIMIZATION; DISTORTION;
D O I
10.1109/TCSI.2024.3399001
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Energy efficiency is of utmost importance in modern applications. Power consumption optimisation could be improved by a comprehensive analytical modeling of the characteristics of critical blocks in a system. Dynamic range (DR) has a strong effect on the power consumption of analog circuits, and is determined by circuit non-linearity and noise level. Noise is well modelled even in deep sub-micron technologies, yet there is a lack of analysis and modeling of the non-linearity. An analytical MOSFET differential pair non-linearity model is presented in this work. The proposed model is universal to a wide range of technologies from long to ultra-deep sub-micron devices, and is valid for all operating regions as it is based on the EKV MOSFET model. Furthermore, a model including drain-voltage-induced non-linearity is also developed, and a concise 3 dB input intercept point (IIP3) formula incorporating the drain induced non-linearity in terms of the voltage gain is presented. The proposed models are validated with DC and AC simulations and measurements.
引用
收藏
页码:4411 / 4419
页数:9
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