IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications

被引：0

作者：

Yan, Aibin ^{[1
]}

Dong, Chen ^{[1
]}

Guo, Xing ^{[1
]}

Song, Jie ^{[1
]}

Cui, Jie ^{[1
]}

Ni, Tianming ^{[2
]}

Girard, Patrick ^{[3
]}

Wen, Xiaoqing ^{[4
]}

机构：

[1] Anhui Univ, Hefei, Peoples R China

[2] Anhui Polytech Univ, Wuhu, Peoples R China

[3] Univ Montpellier, CNRS, Montpellier, France

[4] Kyushu Inst Technol, Fukuoka, Japan

来源：

PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024 | 2024年

基金：

中国国家自然科学基金;

关键词：

Circuit reliability; radiation hardness; soft error tolerance; robust computing; ROBUST;

D O I：

10.1145/3649476.3658761

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modern powerful CMOS chips are usually highly integrated and implemented with aggressively shrunk technology nodes. In radiation environment, under charge-sharing mechanism, one particle striking can simultaneously impact multiple nodes causing double-node-upsets (DNUs) and triple-node-upsets (TNUs). In this paper, we propose an Interlocked Dual-circle Latch Design, namely IDLD, with low cost and TNU recovery for aerospace applications. IDLD consists of four transmission gates and twelve 2-input C-elements (CEs) implemented in 22nm CMOS process. Simulation results demonstrate the complete TNU recovery as well as cost-effectiveness for the proposed IDLD latch.

引用

页码：19 / 24

页数：6

共 44 条

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[8] Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments
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