FPGA Implementation of Sequence Detector for High-Speed PAM4 Wireline Transceiver

To solve the problem of high bit error rate (BER) due to high inter-symbol interference (ISI) in high-speed wireline transceivers, this paper proposes a low-complexity adaptive reduced-state sequence detector (ARSSD). The detector is based on the maximum likelihood sequence detection (MLSD) to reduce the detection bit error rate (BER), adopts the ISI parameter acquisition method based on the zero-forcing algorithm to achieve the adaptive detector parameters, and combines the viterbi algorithm and the set partitioning algorithm to reduce the complexity of operations. The behavioral simulation and the implementation of the hardware circuit are completed in this paper. The experimental results based on the analog front-end and the field programmable gate array (FPGA) show that when the pulse amplitude modulation 4 (PAM4) bit rate is 12 similar to 56Gbps and the channel loss is -5dB similar to-17dB@14GHz, the detection BERs of 32x4 parallel ARSSDs are reduced by two orders of magnitude compared to the conventional decision feedback equalization, which is consistent with the results of the behavioral simulation.