Improved Dual Boost Mid-Point Clamped Five-Level Inverter Topology

被引：1

作者：

Sathik, M. Jagabar ^{[1
]}

Gopinath, N. P. ^{[1
]}

Hota, Arpan ^{[2
]}

Vijayakumar, K. ^{[1
]}

Mekhilef, Saad ^{[3
,4
]}

Agarwal, Vivek ^{[2
]}

机构：

[1] SRM Inst Sci & Technol Kattankulathur, Dept Elect & Elect Engn, Chennai 603203, Tamil Nadu, India

[2] Indian Inst Sci & Technol Bombay, Elect Engn Dept, Mumbai 400076, Maharashtra, India

[3] Swinburne Univ Technol, Sch Sci Comp & Engn Technol, Hawthorn, Vic 3122, Australia

[4] Presidency Univ, Dept Elect & Elect Engn, Bengaluru 560064, India

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2024年 / 71卷 / 06期

关键词：

Topology; Capacitors; Voltage; Inverters; Inductors; Boosting; Through-silicon vias; Dual boost; neutral point clamp; inverter; switched capacitor;

D O I：

10.1109/TCSII.2024.3356171

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief proposes a single-stage dynamic voltage boosting five-level active neutral point clamped (ANPC) inverter topology with continuous input current. The proposed topology can overcome the conventional ANPC five-level inverter drawbacks, such as the requirement of high dc-link voltage and 50% utilization of dc-link capacitors. The proposed topology and its various modes of operation are detailed by highlighting the inductors' charging and discharging periods. Further, the design calculations for sizing the passive components and grid-tied control schemes are discussed. A detailed comparison is presented to show the superiority of the proposed topology compared to other recent topologies. Experimental results from a 1.6 kVA laboratory prototype and simulation results using the MATLAB/Simulink environment are presented to confirm the feasibility of the proposed topology.

引用

页码：3221 / 3225

页数：5

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