RISCALAR: A Cycle-Approximate, Parametrisable RISC-V Microarchitecture Explorer & Simulator

Riscalar is a highly parameterisable, extensible, and modular computer architecture simulation tool designed for the RISC-V ISA. The ability of Riscalar to explore a large design space with configurable pipeline widths, execution orders, functional units, cache sizes, and branch predictors differentiates it from other RISC-V educational simulators. It is capable of simulating user-designed programs through standard crosscompilation tools, and can be used to explore the relationship between processor microarchitecture, compiler optimizations, and program performance. This paper details the design and implementation of Riscalar using Rust, highlighting the abstractions made to implement a cycle-approximate simulator.