Evolution of Hardware-Aware Neural Architecture Search on the Edge

被引:0
作者
Richey, Blake [1 ]
Clay, Mitchell [2 ]
Grecos, Christos [2 ]
Shirvaikar, Mukul [1 ]
机构
[1] Univ Texas Tyler, Dept Elect Engn, Tyler, TX 75799 USA
[2] Arkansas State Univ, Dept Comp Sci, Jonesboro, AR USA
来源
REAL-TIME IMAGE PROCESSING AND DEEP LEARNING 2023 | 2023年 / 12528卷
关键词
Neural Architecture Search; AI on the Edge; Edge computing; Evolutionary Strategies; Deep Learning;
D O I
10.1117/12.2664894
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
Neural Architecture Search (NAS) is a method of autonomously designing deep learning models to achieve top performance for tasks such as data classification and data retrieval by using defined search spaces and strategies. These strategies have demonstrated improvements in a variety of tasks over ad-hoc deep neural architectures, but have presented unique challenges related to bias in search spaces, the intensive training requirements of various search strategies, and inefficient model performance evaluation. These challenges have been a primary focus for NAS research until recently. However, artificial intelligence (AI) on the edge has emerged as a significant area of research and producing models that achieve top performance on small devices with limited resources has become a priority. NAS research has primarily been focused on improving models by using more diverse search spaces, improving search strategies, and evaluating models faster. A limitation when applied to edge devices is that NAS has historically been finding superior deep neural networks that have become increasingly more difficult to port to embedded devices due to memory limitations, computational bottlenecks, latency requirements, and power restrictions. In recent years, researchers have begun to consider these limitations and develop methods for porting deep neural networks to these embedded devices, but few methods have incorporated the device itself in the training process efficiently. In this paper, we compile a list of methods actively being explored and discuss their limitations. We also present our evidence in support of the use of genetic algorithms as a method for hardware-aware NAS that efficiently considers hardware, power, and latency requirements during training.
引用
收藏
页数:9
相关论文
共 23 条
[1]  
Cai Ermao, Neuralpower: Predict and deploy energy-efficient convolutional neural networks
[2]  
Cai H, 2020, Arxiv, DOI arXiv:1908.09791
[3]  
Courbariaux M, 2016, Arxiv, DOI arXiv:1602.02830
[4]   Grow and Prune Compact, Fast, and Accurate LSTMs [J].
Dai, Xiaoliang ;
Yin, Hongxu ;
Jha, Niraj K. .
IEEE TRANSACTIONS ON COMPUTERS, 2020, 69 (03) :441-452
[5]  
Dai Xiaoliang, 2017, IEEE Transactions on Computers
[6]   LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks [J].
Ding, Ruizhou ;
Liu, Zeye ;
Shi, Rongye ;
Marculescu, Diana ;
Blanton, R. D. .
PROCEEDINGS OF THE GREAT LAKES SYMPOSIUM ON VLSI 2017 (GLSVLSI' 17), 2017, :35-40
[7]  
Ding RZ, 2018, ASIA S PACIF DES AUT, P1, DOI 10.1109/ASPDAC.2018.8297274
[8]   DPP-Net: Device-Aware Progressive Search for Pareto-Optimal Neural Architectures [J].
Dong, Jin-Dong ;
Cheng, An-Chieh ;
Juan, Da-Cheng ;
Wei, Wei ;
Sun, Min .
COMPUTER VISION - ECCV 2018, PT XI, 2018, 11215 :540-555
[9]   SqueezeNext: Hardware-Aware Neural Network Design [J].
Gholami, Amir ;
Kwon, Kiseok ;
Wu, Bichen ;
Tai, Zizheng ;
Yue, Xiangyu ;
Jin, Peter ;
Zhao, Sicheng ;
Keutzer, Kurt .
PROCEEDINGS 2018 IEEE/CVF CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION WORKSHOPS (CVPRW), 2018, :1719-1728
[10]   MorphNet: Fast & Simple Resource-Constrained Structure Learning of Deep Networks [J].
Gordon, Ariel ;
Eban, Elad ;
Nachum, Ofir ;
Chen, Bo ;
Wu, Hao ;
Yang, Tien-Ju ;
Choi, Edward .
2018 IEEE/CVF CONFERENCE ON COMPUTER VISION AND PATTERN RECOGNITION (CVPR), 2018, :1586-1595