An Area and Energy-Efficient SRAM Based Time - Domain Compute-In-Memory Architecture For BNN

In this paper, we present an area and energy efficient SRAM based time-domain compute-in-memory (TDCIM) architecture to accelerate binary neural networks (BNNs). We have proposed an area efficient time-domain multiplication bitcell (MC). The proposed MC is 1.5x times area efficient than state-of-the- art. The proposed TDCIM focuses on improving the energy efficiency of the multiplication and accumulation (MAC) operation. It achieves 1.6x higher energy efficiency compared to state of the art. The work uses a time domain computing approach by introducing a specific delay which is equivalent to the MAC operation performed. A proposed robust 10T1C SRAM bit cell has been used to perform in-memory XNOR operation. A time to digital converter (TDC) has been used instead of analog to digital converter (ADC) to save the power consumption. The designed architecture has been implemented using a 45 nm CMOS technology, resulting in the development of a 25x32 SRAM CIM macro. Post layout simulation results demonstrate the proposed architecture achieved an energy efficiency of 877.32 TOPS/W at VDD of 0.9 V. The architecture achieves an inference accuracy of 98.68% on the MNIST dataset.