A comprehensive review of time skew background calibration and mitigation techniques in high-speed time-interleaved analog-to-digital converters

A significant challenge in designing high-speed time-interleaved ADCs (TI-ADCs) is the presence of time skew mismatch, resulting from uneven sampling across different channels and constituting a significant source of error. This error can be mitigated either by employing samplers unaffected by time skew or by employing foreground/background time skew calibration methods. Considering that the complexity of time skew calibration can complicate analog-to-digital converter (ADC) design, simpler techniques are essential, particularly with the development of higher-speed ADCs using smaller technology nodes. This paper offers a comprehensive examination of various techniques applied in TI-ADCs to address time skew-related issues. We will explore skew-tolerant sampling techniques to alleviate time skew errors, followed by an exploration of background time skew calibration methods. The primary focus of this paper centers on background time skew calibration techniques, which have become integral to improving the dynamic performance of high-speed TI-ADCs. The main background time skew calibration techniques to be reviewed include error injection techniques, reference ADC-based techniques, input slope estimation, autocorrelation-based techniques, and variance-based techniques. A significant challenge in designing high-speed time-interleaved ADCs, shown in the first figure, is the presence of time skew mismatch, resulting from uneven sampling across different channels and constituting a significant source of error as shown in the second figure. We will explore skew-tolerant sampling techniques to alleviate time skew errors, followed by an exploration of background time skew calibration methods. The main background time skew calibration techniques to be reviewed include error injection techniques, reference ADC-based techniques, input slope estimation, autocorrelation-based techniques, and variance-based techniques. Quantitative comparison of these calibration techniques, shown in Figures 3-9, reveals derivative-based and variance-based TI-ADCs exhibiting superior Schreier figure of merit (FoMs) up to a Nyquist sampling rate of 1 GHz. However, error injection-based and reference ADC-based TI-ADCs demonstrate higher FoMs on average from 1 to 10 GHz Nyquist sampling rates. Correlation-based techniques have emerged as preferable over the past decade due to their ability to balance input frequency and effective number of bits (ENOB). Variance-based techniques demonstrate the weakest balance between input frequency and effective number of bits (ENOB), whereas the remaining calibration techniques fall somewhere in between. Upon meticulous examination of designs with an SNDR exceeding 50 dB, it becomes evident that correlation-based techniques exhibit the least energy-efficient structure, while other calibration techniques show similar energy efficiency. Furthermore, correlation-based TI-ADCs are notably capable of providing a compelling combination of high bandwidth and higher SNDR. However, it is worth noting that despite their numerous benefits, correlation-based techniques are the most inefficient in terms of chip area consumption. image