Investigation of Reliability Issues in a hybrid Extended Dual Source Double Gate Tunnel FET

被引:0
作者
Ghosh, P. [1 ,2 ]
Pratap, S. [1 ,2 ]
Tripathi, S. [1 ,2 ]
Yashwanth, K. [1 ,2 ]
机构
[1] Indian Inst Informat Technol Ranchi, Dept Elect & Commun Engn, Ranchi, Jharkhand, India
[2] Indian Inst Technol, Dept Elect Engn, Delhi, India
关键词
Dual gate; Dual source; Subthreshold swing (SS); Tunnel field-effect transistor (TFET); Tunneling; TRANSISTOR; TFETS;
D O I
10.1080/03772063.2024.2370962
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents the design and analysis of an enhanced tunnel field-effect transistor (TFET) structure. The proposed structure comprises a dual source and a double gate, aiming to enhance the DC characteristics of the TFET. The dual source concept is used in the structure with two homogeneous gates, which play a major role in boosting the tunneling parameters. It also examines the affectability of source dimensions and drain doping on the performance of the proposed device. Furthermore, we have compared our proposed structure with the single source device. The proposed device after optimization exhibits an extraordinary ION/IOFF ratio of 2.33 x 1013, with an IOFF of 6.25 x 10-19A/mu m, and decent Ion of 1.46 x 10-5A/mu m along with a subthreshold swing (SS) of 43 mV/dec. The device characteristics have been analyzed in the presence of interface traps. The electrical parameters have been quantified against various types and concentrations of traps. The performance of the proposed device has been compared with the existing TFET structures.
引用
收藏
页码:8255 / 8262
页数:8
相关论文
共 27 条
[1]   Analysis of III-V material-based dual source T-channel junction-less TFET with metal implant for improved DC and RF performance [J].
Anam, Aadil ;
Amin, S. Intekhab ;
Prasad, Dinesh ;
Kumar, Naveen ;
Anand, Sunny .
MICRO AND NANOSTRUCTURES, 2023, 181
[2]   Design and Analysis of Dual Source Vertical Tunnel Field Effect Transistor for High Performance [J].
Badgujjar, Soniya ;
Wadhwa, Girish ;
Singh, Shailendra ;
Raj, Balwinder .
TRANSACTIONS ON ELECTRICAL AND ELECTRONIC MATERIALS, 2020, 21 (01) :74-82
[3]   TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model [J].
Biswas, Arnab ;
Dan, Surya Shankar ;
Le Royer, Cyrille ;
Grabinski, Wladyslaw ;
Ionescu, Adrian M. .
MICROELECTRONIC ENGINEERING, 2012, 98 :334-337
[4]   Analog/RF Performance of T-Shape Gate Dual-Source Tunnel Field-Effect Transistor [J].
Chen, Shupeng ;
Liu, Hongxia ;
Wang, Shulong ;
Li, Wei ;
Wang, Xing ;
Zhao, Lu .
NANOSCALE RESEARCH LETTERS, 2018, 13
[5]   Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec [J].
Choi, Woo Young ;
Park, Byung-Gook ;
Lee, Jong Duk ;
Liu, Tsu-Jae King .
IEEE ELECTRON DEVICE LETTERS, 2007, 28 (08) :743-745
[6]   DESIGN OF ION-IMPLANTED MOSFETS WITH VERY SMALL PHYSICAL DIMENSIONS [J].
DENNARD, RH ;
GAENSSLEN, FH ;
YU, HN ;
RIDEOUT, VL ;
BASSOUS, E ;
LEBLANC, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1974, SC 9 (05) :256-268
[7]   Low-frequency noise analysis of heterojunction SELBOX TFET [J].
Ghosh, P. ;
Bhowmick, B. .
APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING, 2018, 124 (12)
[8]   Performance analysis and digital application of vertical L-pattern dual tunnel diode TFET [J].
Ghosh, Puja .
MICROELECTRONICS JOURNAL, 2022, 129
[9]   Investigation of Electrical Characteristics in a Ferroelectric L-Patterned Gate Dual Tunnel Diode TFET [J].
Ghosh, Puja ;
Bhowmick, Brinda .
IEEE TRANSACTIONS ON ULTRASONICS FERROELECTRICS AND FREQUENCY CONTROL, 2020, 67 (11) :2440-2444
[10]   Analysis of kink reduction and reliability issues in low-voltage DTD-based SOI TFET [J].
Ghosh, Puja ;
Bhowmick, Brinda .
MICRO & NANO LETTERS, 2020, 15 (03) :130-135