A 72-channel Resistive-sensor Interface IC with High Energy Efficiency and a Wide Input Range

This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC includes 8 sensor oscillators and 8 time-to-digital converters (TDCs), and each set of a sensor oscillator and a TDC is time-multiplexed to measure from 9 sensors. Consequently, it attains impressive energy efficiency of 310 pJ per channel. Employing a time-domain interface approach, the IC directly converts sensor resistance into time, extending its measurement capabilities up to 10 MO. It also takes advantage of a high-energy-efficiency phase-locked loop (PLL), resulting in a high signal-to-quantization-noise ratio (SQNR) that reaches the intrinsic signal-to-noise ratio (SNR) of the sensor oscillator. This results in an effective number of bits (ENOB) of 9.3 bits when 310 pJ is consumed for each channel. The ENOB can be adjusted through external FPGA control, and the maximum ENOB achieved is 14.1 with an oversampling ratio (OSR) of 256. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015mm2, consumes only 15.07 mu W per channel, resulting in a channelspecific Walden figure of merit (FoM) of 0.48 pJ per conversion step. Furthermore, by adjusting the OSR, the IC achieves an outstanding Schreier FoM of 159.8 dB in scenarios requiring high resolution.