A 30.5-to-31 GHz Sampling PLL With DoubleEdge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and-253.6-dB FoM in a 0.047mm2 Area

被引：0

作者：

Dong, Zhicheng ^{[1
]}

Zhao, Xiaoteng ^{[1
]}

Huang, Weitan ^{[1
]}

Gao, Yuan ^{[1
]}

Sun, Depeng ^{[1
]}

Liu, Shubin ^{[1
]}

Yang, Lihong ^{[1
]}

Zhu, Zhangming ^{[1
]}

机构：

[1] Xidian Univ, Sch Integrated Circuitss, Key Lab Analog Integrated Circuits & Syst, Minist Educ, Xian 710071, Peoples R China

来源：

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年

基金：

中国国家自然科学基金;

关键词：

CMOS; double-edge sampling phase detector (DSPD); implicit common-mode; low jitter; sampling PLL; phase noise; reference spur; self-retimed MMD; VCO;

D O I：

10.1109/ISCAS58744.2024.10558529

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents an integer-N sampling phaselocked loop (S-PLL) characterized by both low jitter and low spur. The design integrates a high-gain double-edge sampling phase detector (PD) and a self-retimed multi-modulus divider (MMD) aimed at mitigating the in-band noise. Furthermore, it features a compact implicit common-mode voltage-controlled oscillator (VCO) with a second harmonic tuning tailored for noise reduction. The proposed S-PLL, fabricated in a 28-nm CMOS technology, operates at 31 GHz with a 250-MHz reference. The measured RMS jitter is 39.69 fs integrated from 10 kHz to 100 MHz, with a reference spur of -63.2 dBc. The proposed PLL achieves a figure-of-merit (FoM) of -253.6 dB with a 28-mW power and a 0.047-mm(2) area.

引用

页数：5