CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security

被引:0
|
作者
Xu, Zihan [1 ]
Yin, Lingfeng [1 ]
Lyu, Yongqiang [2 ]
Wang, Haixia [2 ]
Qu, Gang [3 ,4 ]
Wang, Dongsheng [1 ]
机构
[1] Tsinghua Univ, Dept Comp Sci & Technol, Beijing 100084, Peoples R China
[2] Tsinghua Univ, Beijing Natl Res Ctr Informat Sci & Technol, Beijing 100084, Peoples R China
[3] Univ Maryland, Dept Elect & Comp Engn, College Pk, MD 20742 USA
[4] Univ Maryland, Syst Res Inst, College Pk, MD 20742 USA
基金
中国国家自然科学基金;
关键词
D O I
暂无
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Defending cache timing side-channels has become a major concern in modern secure processor designs. However, a formal method that can completely check if a given cache design can defend against timing side-channel attacks is still absent. This study presents CacheGuard, a behavior model checker for cache timing side-channel security. Compared to current state-of-the-art prose rule-based security analysis methods, CacheGuard covers the whole state space for a given cache design to discover unknown side-channel attacks. Checking results on standard cache and state-of-the-art secure cache designs discovers 5 new attack strategies, and potentially makes it possible to develop a timing side channel-safe cache with the aid of CacheGuard.
引用
收藏
页码:19 / 24
页数:6
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