Feedback Enhanced Area-Efficient ESD Power Clamp Circuit

被引：1

作者：

Yang, Zhaonian ^{[1
]}

Wei, Liyao ^{[1
]}

Kai, Gaoxiang ^{[1
]}

Pu, Shi ^{[2
]}

Wang, Biyun ^{[1
]}

Liu, Jing ^{[1
]}

Yang, Yuan ^{[1
]}

Yu, Ningmei ^{[1
]}

机构：

[1] Xian Univ Technol, Shaanxi Key Lab Complex Syst Control & Intelligent, Yanan 710048, Peoples R China

[2] Xian Xiangteng Microelect Co Ltd, Xian 710068, Peoples R China

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2024年 / 71卷 / 08期

基金：

中国国家自然科学基金;

关键词：

Clamps; Electrostatic discharges; Layout; MOSFET; Logic gates; MOSFET circuits; Integrated circuit modeling; Clamp circuit; electrostatic discharge (ESD); feedback; parasitic capacitance; PROTECTION;

D O I：

10.1109/TED.2024.3418305

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this article, a feedback-enhanced power clamp circuit for ON-chip electrostatic discharge (ESD) protection is proposed and verified using silicon data. To conserve the layout area, the conventional MOSFET capacitor is replaced with a parasitic n-well/p-substrate junction capacitor to detect ESD events. The feedback mechanism is carefully designed to prolong the turn-on duration of the clamp circuit, thereby enhancing the ESD robustness. Experimental results show that the proposed clamp, featuring a 2000 $\mu$ m wide clamping MOSFET, achieves a comparable transmission line pulsing (TLP) failure current of approximately 9.5 A when compared to the conventional RC triggered counterparts. Simultaneously, it reduces the layout area, enhances false triggering immunity, and enhances the robustness during long pulse events.

引用

页码：4504 / 4509

页数：6

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