The study of lithographic variation in resistive random access memory

被引:2
作者
Zhang, Yuhang [1 ,2 ]
He, Guanghui [1 ,2 ]
Zhang, Feng [3 ]
Li, Yongfu [1 ,2 ]
Wang, Guoxing [1 ,2 ]
机构
[1] Shanghai Jiao Tong Univ, Dept Micronano Elect, Shanghai 200240, Peoples R China
[2] Shanghai Jiao Tong Univ, MoE Key Lab Artificial Intelligence, Shanghai 200240, Peoples R China
[3] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
基金
美国国家科学基金会;
关键词
layout; lithography; process variation; resistive random access memory; PROXIMITY CORRECTION; RRAM; CIRCUIT; IMPACT; DEVICE; ARRAY;
D O I
10.1088/1674-4926/45/5/052303
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
Reducing the process variation is a significant concern for resistive random access memory (RRAM). Due to its ultra-high integration density, RRAM arrays are prone to lithographic variation during the lithography process, introducing electrical variation among different RRAM devices. In this work, an optical physical verification methodology for the RRAM array is developed, and the effects of different layout parameters on important electrical characteristics are systematically investigated. The results indicate that the RRAM devices can be categorized into three clusters according to their locations and lithography environments. The read resistance is more sensitive to the locations in the array (similar to 30%) than SET/RESET voltage (<10%). The increase in the RRAM device length and the application of the optical proximity correction technique can help to reduce the variation to less than 10%, whereas it reduces RRAM read resistance by 4x, resulting in a higher power and area consumption. As such, we provide design guidelines to minimize the electrical variation of RRAM arrays due to the lithography process.
引用
收藏
页数:11
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