` Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms

被引：0

作者：

Verstov, Vladimir ^{[1
]}

Shakhnov, Vadim ^{[1
]}

Zinchenko, Lyudmila ^{[1
]}

机构：

[1] Ul Baumanskays 2 Ya,5, Moscow 105005, Russia

来源：

TECHNOLOGICAL INNOVATION FOR COLLECTIVE AWARENESS SYSTEMS | 2014年 / 423卷

关键词：

VLSI; Layout; Double Pattering; Parallel Algorithms; High-Performance Computing; Radiation Hardening;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

In the paper silicon on insulator layout decomposition algorithms for the double patterning lithography on high performance computing platforms are discussed. Our approach is based on the use of a contradiction graph and a modified concurrent breadth-first search algorithm. We evaluate our technique on both real-world and artificial test cases including non-Manhattan geometry. Experimental results show that our soft computing algorithms decompose layout successfully and a minimal distance between polygons in layout is increased.

引用

页码：543 / 550

页数：8

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