Introduction of Digital System-In-Package building block for space applications

被引：0

作者：

Garcia, Hugo ^{[1
,2
]}

Jochem, Helene ^{[1
,2
]}

Venet, Norbert ^{[1
,2
]}

Rocci, Mirko ^{[1
,2
]}

Dabas, Andres Matias ^{[1
,2
]}

Sollecchia, Luca ^{[1
,2
]}

Juul, Poul ^{[3
]}

Ankeraa, Kim ^{[3
]}

Mayr, Monique ^{[4
]}

Scalmati, Paolo ^{[5
]}

Cucinella, Giovanni ^{[6
]}

机构：

[1] Thales Alenia Space, France 26 Ave Jean Francois Champollion, F-31100 Toulouse, France

[2] Via Gian Domenico Cassini 6, I-67100 Laquila, AQ, Italy

[3] HYTEK, Sofievej 61, DK-9000 Aalborg, Denmark

[4] Panason Ind Devices Mat Europe GmbH, Ennshafenstr 30, A-4470 Enns, Austria

[5] SOMACIS SPA, Via Jesina 17, I-60022 Castelfidardo, AN, Italy

[6] IMT, Via Carlo Bartolomeo Piazza 30, I-00161 Rome, Italy

来源：

2024 IMAPS NORDIC CONFERENCE ON MICROELECTRONICS PACKAGING, NORDPAC 2024 | 2024年

关键词：

SIP; Substrate; PCB; HDI; design; fan-out; Space;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This work presents a comprehensive investigation into the design, manufacturing, and testing of a complex System-in-Package (SIP) intended for space applications. The SIP consists of multiple dies (x6) with bump counts (>2000) and pitches (200 mu m), necessitating careful consideration of substrate stack-up configurations and electrical behavior. Through simulations and experimental testing, various stack-up configurations were evaluated to achieve desired parameters, including a data velocity of 25GHz @ -30dB. As SiP with organic substrate technology is not introduced in the space market, test flow procedures were defined, combining ECSS, IPC and MIL standards with tailored groups to validate SIP technology, and coupons were designed for thorough testing. Manufacturing and inspection processes were conducted to ensure substrate quality and dimensional accuracy. Furthermore, chip assembly tests were performed to assess the warpage behavior of the substrate to identify the most appropriate packaging solution. Overall, this study provides valuable insights into the development and qualification of complex SIPs for space applications, highlighting the importance of thorough testing and continuous improvement in ensuring reliability and performance in harsh environments.

引用

页数：6

共 12 条

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[2] [Anonymous], 2012, MIL-STD-883H-Department of defense test method standard: Microcircuits
[3] [Anonymous], 2012, IPC 6012D-Qualification and Performance Specification for Rigid Printed Boards
[4] Effects of Voiding on the Degradation of Microvias in High Density Interconnect Printed Circuit Boards Under Thermomechanical Stresses
Bakhshi, Roozbeh
Azarian, Michael H.
Pecht, Michael G.
[J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2014, 4 (08): : 1374 - 1379
[5] Birch Bill, 2017, Reliability testing of multiple level microvia structures following exposure to lead-free assembly
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[7] Ho P. S., Study on Factors Affecting Underfill Flow and Underfill Voids in a Large-die Flip Chip Ball Grid Array (FCBGA) Package
[8] Hsu Jim, SiP Module Warpage Characterization and Simulation Study
[9] Jochem H., Innovative system in Package building blocs for future space
[10] Loh Wei Keat, Recent Trends of Package Warpage and Measurement Metrologies

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