Analysis of Reconfiguration Delay in Heterogeneous Systems-on-Chip via Traffic Injection

被引：1

作者：

Valente, Giacomo ^{[1
]}

Muttillo, Vittoriano ^{[2
]}

Federici, Fabio ^{[3
]}

Pomante, Luigi ^{[1
]}

Di Mascio, Tania ^{[1
]}

机构：

[1] Univ Aquila, Dept Informat Engn Comp Sci & Math, I-67100 Laquila, Italy

[2] Univ Teramo, Dept Polit Sci, I-64100 Teramo, Italy

[3] Collins Aerosp, Appl Res & Technol, I-00185 Rome, Italy

来源：

IEEE EMBEDDED SYSTEMS LETTERS | 2024年 / 16卷 / 02期

关键词：

Delays; Field programmable gate arrays; Real-time systems; Random access memory; Interference channels; Quality of service; Memory management; Dynamic reconfiguration; field-programmable gate array (FPGA); system-on-chip (SoC);

D O I：

10.1109/LES.2023.3305401

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Modern real-time systems started leveraging runtime reconfigurable architectures to reduce size, weight, and power while ensuring predictability. However, the time to reconfigure a platform (referred to as reconfiguration delay) is non-negligible and subject to fluctuations caused by conflicts in accessing shared components during the reconfiguration process. Different from existing solutions that impact either system resources or system performance, in this letter, we propose an approach, together with its supporting tools, allowing to characterize the reconfiguration delay and to be able to capture and produce evidence of the actual impact of the resource contention. In addition, we report the experiments of the proposed approach in a representative configuration on a Xilinx Zynq Ultrascale+ MPSoC; results show that conflicts can impact the reconfiguration delay at most by 230%.

引用

页码：162 / 165

页数：4