Performance investigation of ferroelectric L-shaped tunnel FET with suppressed corner tunneling for low power applications

In this work, a ferroelectric L-shaped tunnel FET (FE-LSTFET) is introduced to offer improvement in various DC and analog/high-frequency parameters. In this design, the incorporated FE layer enhances the vertical electric field at the source -channel interface, which improves the tunneling rate of charge carriers during the ON -state. The effect of negative capacitance (NC) and L-shaped N + pocket causes dominance of vertical tunneling over corner tunneling (mainly at low gate voltages), which in turn reduces the transition voltage and current from 0.85 to 0.25 V and 1.2 x 10 -8 to 5.67 x 10 -11 A/ mu m respectively, thereby improving parameters such as I ON , I OFF, and SS avg . Further, optimization of the thickness and doping concentration helps to keep the N + pocket in fully depleted mode and consequently, I ON /I OFF is increased from 0.3 x 10 12 to 1.2 x 10 14 and SS avg is reduced from 52 to 30 mV/decade. Subsequently, NC parameters such as remanent polarization (P r ) and coercive electric field (E c ) are optimized to increase the memory window, which further improves the read margin of FE-LSTFET as a memory device. Furthermore, TCAD-based simulation results show that optimizing the FE thickness improves I ON and I OFF in the order of - 1 and - 2, respectively compared to those of C-LSTFET. With an optimum drainoverlap length, I OFF is shown to reduce from 6.6 x 10 -17 to 5.43 x 10 -19 A/ mu m due to a reduction in the SRH generation rate of the charge carriers. Despite the degradation in C gg due to drain -overlap by the stack of FE and SiO 2 layers, a significant increase in e-BTBT helps in achieving a transconductance of 2.48 x 10 -4 S/ mu m, thus leading to a large cut-off frequency of 34.12 GHz. Next, analysis of the FE-LSTFET-based inverter shows significant improvements in several parameters including propagation delay and full swing. Moreover, FE-LSTFET shows more reluctance to self -heating effects than C-LSTFET as I ON /I OFF is increased by an order of - 3 at 500 K. Lastly, the performance of FE-LSTFET is benchmarked with existing TFET designs indicating that FE-LSTFET is suitable as a high-speed and low -power memory device.