A floating-point multiplier based on angle representation method

This article proposes a novel angle representation method for floating-point number, which eliminates the need for DSP (Digital Signal Processor) resources and reduces the resource usage when performing floating-point multiplication. Compared with the implementation of floating-point multiplier using IP cores, the implementation of approximate multiplication based on lookup tables can achieve an average reduction of 58.2% in LUTs (look-up tables) and an average increase of 20.4% in frequency for mantissa widths ranging from 3 to 12 bits. Additionally, it can also save an average of 23.2% in registers. Analysis of PDP (power-delay product)/LUT to MRED (mean relative error distance)/PRED (probability of relative error distance) among other approximate multipliers shows that the proposed design extends the Pareto front. At last, simulation of a three-level inverter is implemented to verify the effectiveness of the multiplier. This article proposes a novel angle representation method for floating-point number, which eliminates the need for DSP resources and reduces the resource usage when performing floating-point multiplication. image