Effective Hardware Implementation of Convolution with Binary Sequences

被引：0

作者：

Minenkov, Dmitrii ^{[1
]}

Voznesensky, Alexander ^{[2
]}

Wang, Dianhui ^{[1
]}

Kaplun, Dmitrii ^{[1
]}

机构：

[1] China Univ Min & Technol, Artificial Intelligence Res Inst, Xuzhou, Jiangsu, Peoples R China

[2] St Petersburg Electrotech Univ LETI, Dept Automat & Controll Proc, St Petersburg, Russia

来源：

2024 13TH MEDITERRANEAN CONFERENCE ON EMBEDDED COMPUTING, MECO 2024 | 2024年

关键词：

DSSS; FIR filter; convolution; binary coefficients; FPGA and ASIC implementation; binary neural network;

D O I：

10.1109/MECO62516.2024.10577796

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Despite the development of communication systems with Orthogonal frequency-division multiplexing (OFDM) technology, the Direct Sequence Spread Spectrum (DSSS) technique is useful and widely employed in many applications. The main element of the DSSS receiver is a matched (correlation) filter. In this paper, we consider the structures of devices that realize the convolution of a signal with a binary sequence. A comparison of hardware costs for FPGA implementation with the use of the Xilinx Vivado software tool and for ASIC implementation with the use of the YoSYS software tool is presented. Experimental results show that the proposed solution is effective and outperforms the existing ones in terms of hardware resources usage and device area.

引用

页码：94 / 97

页数：4