Effective Hardware Implementation of Convolution with Binary Sequences

Despite the development of communication systems with Orthogonal frequency-division multiplexing (OFDM) technology, the Direct Sequence Spread Spectrum (DSSS) technique is useful and widely employed in many applications. The main element of the DSSS receiver is a matched (correlation) filter. In this paper, we consider the structures of devices that realize the convolution of a signal with a binary sequence. A comparison of hardware costs for FPGA implementation with the use of the Xilinx Vivado software tool and for ASIC implementation with the use of the YoSYS software tool is presented. Experimental results show that the proposed solution is effective and outperforms the existing ones in terms of hardware resources usage and device area.