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Formation of Polymer Insulation Layer (Liner) on Through Silicon Vias (TSV) with High Aspect Ratio over 5:1 by Direct Spin Coating
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2016 IEEE 66TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC),
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Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects
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2010 PROCEEDINGS 60TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC),
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