GOLDS: Genetic Algorithm-based Optimization of Custom FPGA Architecture Layout Design for Secure Silicon

Modern FPGAs, equipped with heterogeneous blocks (H-blocks) offer design flexibility, enabling the implementation of complex designs with minimal effort. Custom-embedded fabric in System-on-a-Chip (SoC) has recently been envisioned to secure an IP block through the entire flow from design to manufacture, which involves multiple vendors. Hence, new design strategies for deducing efficient embedded-FPGA (eFPGA) architecture blocks targeted toward specific workloads need to be investigated. This work applied Genetic Algorithm (GA) to generate the most optimal H-block-defined FPGA layout to achieve the best hardware objectives, including critical path delay, resources utilized, and power consumed for the benchmark under test. The strategic placement of memory, digital signal processor (DSP) slices, and configurable logic blocks (CLBs) targeted for attaining minimum area-delay-product (ADP) for the benchmark-under-test, on the given layout forms the crux of this work. This novel framework was applied to different machine learning (ML) and non-ML benchmarks to characterize its performance against other state-of-the-art (SOTA) FPGA architectural layout designs. The proposed work showcases a maximum of 35% ADP gain for one of the benchmark design runs over the SOTA-designed layout. The ideal fabric layout architecture is a step towards securing IP on an eFPGA block, which is not disclosed to other vendors and configured as per the targeted workload post-fabrication of the chip.