A 14-bit 6GS/s DAC Achieving >65dBc SFDR with Bilateral Output Impedance Compensation in 22nm CMOS

被引：0
作者：
Xing, Xipeng [1 ]
Huang, Qiji [2 ]
Chen, Tinghua [2 ]
Feng, Haigang [2 ]
Wang, Zhongfeng [1 ]
机构：
[1] Sun Yat Sen Univ, Sch Integrated Circuits, Shenzhen, Guangdong, Peoples R China
[2] Tsinghua Univ, Shenzhen Int Grad Sch, Shenzhen, Guangdong, Peoples R China
来源：
2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年
基金：
中国国家自然科学基金;
关键词：
Bilateral compensation; current steering; digital-to-analog converter (DAC); output impedance; calibration; GS/S; DBC; IM3;
D O I：
10.1109/ISCAS58744.2024.10557879
中图分类号：
TP39 [计算机的应用];
学科分类号：
081203 ; 0835 ;
摘要：
A 14-bit 6.0-GS/s current-steering digital-to-analog converter (DAC) is presented in this paper. A bilateral output impedance compensation (BOIC) technique is proposed to suppress DAC nonlinearity induced by cell finite output impedance, which is compact, effective and power-efficient. Compensation networks are implemented by two NMOS transistors with code-dependent gate voltage. Furthermore, the calibration structure is improved to enable DAC cell bidirectional calibration, by designing the calibration DAC with a constant current source load. Simulation results in 22-nm CMOS show that The DAC achieves >65-dBc spurious-free dynamic range (SFDR) over the entire Nyquist bandwidth, with a 1.1V supply and an output swing over 0.9Vpp. The DAC core power consumption is only 37mW, showing its merits over state-of-the-art designs.
引用
收藏
页数：5
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