Cryogenic CMOS RF Circuits: A Promising Approach for Large-Scale Quantum Computing

This brief presents a brief overview of cryogenic CMOS circuits for large-scale quantum computing, especially the cryogenic RF circuits from the functional blocks to system-level ASICs. To start with, the cryogenic CMOS device characteristics of the process nodes ranging from 180nm to 5nm are examined and compared. The cryogenic RF blocks including the LNA and VCO in the recent literature are then briefly reviewed, with highlights on the key design points. The evolution of state-of-the-art system-level quantum interface cryogenic circuits is given including the design requirements, top-level architectures, and design considerations. The future directions and trends are also briefly discussed, aiming to promote the integration level of quantum computing.