A Constant-Quiescent-Current and Fast-Transient CL-LDO with 99.99% Efficiency Using Dynamic Embedded Slew-Rate Enhancement Circuit

被引：0

作者：

Wang, Yue ^{[1
]}

Guo, Aiying ^{[1
]}

Zhang, Jianhua ^{[1
]}

Liu, Jingjing ^{[1
]}

机构：

[1] Shanghai Univ, Sch Microelect, Shanghai, Peoples R China

来源：

2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 | 2024年

关键词：

capacitor-less low dropout regulator; slew-rate; fast-transient; high current efficiency;

D O I：

10.1109/ISCAS58744.2024.10558479

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

This paper presents a low constant quiescent current and fast transient response capacitor-less low dropout regulator (CL-LDO) with high current efficiency, achieved using a dynamic slew-rate enhancement (SRE) circuit. The proposed CL-LDO achieves a fast transient response without requiring additional current under heavy loads, enabling a peak current efficiency of 99.99%. Designed using a 55-nm standard CMOS process, the CL-LDO consumes a quiescent current of 10 mu A. It can deliver 0.2-100 mA of load current at a 1.0-V output from a 1.2-V to 1.5-V supply voltage. Additionally, it achieves a settling time of 0.418 mu s and an overshoot/undershoot voltage of 74 mV/166 mV for load steps ranging from 0.2 mA to 100 mA, with an edge time of 0.1 mu s.

引用

页数：5