Dual-bootstrapping gate driver circuit design using IGZO TFTs

被引:0
|
作者
Liao, Congwei [1 ]
Zheng, Xin [2 ]
Zhang, Shengdong [2 ]
机构
[1] Shenzhen Technol Univ, Coll Integrated Circuits & Optoelect Chips, Shenzhen 518118, Peoples R China
[2] Peking Univ, Shenzhen Grad Sch, Sch Elect & Comp Engn, Shenzhen 518055, Peoples R China
关键词
Gate driver; OLED; LCD; Display; IGZO TFT; Falling time; Narrow border; Fast speed; High reliability; THIN-FILM-TRANSISTOR; LOW-POWER; SI; ARRAY;
D O I
10.1016/j.displa.2024.102772
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
To promote the integration of thin-film transistor (TFT) gate driver circuit technology into high-resolution largesize display application with narrow bezel, achieving high speed is a critical challenge. This paper proposed a dual-bootstrapping TFT integrated gate driver circuit for large-size display. The over-drive voltage of the driving TFT was increased both at the rising and falling edges of the output waveforms. To validate the circuit feasibility, the proposed circuit was fabricated using amorphous indium-gallium-zinc-oxide (a-IGZO) TFT technology and measured in terms of transient response with cascaded stages and reliability tests over long operating time. Compared to conventional approaches, the proposed gate driver demonstrates a 39 % reduction in the falling time as well as compact layout. Therefore, the proposed gate driver schematic is well-suited for large-size display applications that involves heavy resistance-capacitance (RC) loadings and require high resolution above 8 K.
引用
收藏
页数:5
相关论文
共 50 条
  • [31] Enhanced current mirror circuit by dual-gate coplanar amorphous InGaZnO TFTs
    Rahaman, Abidur
    Adhikary, Apurba
    Hossain, Mohammad Amzad
    Islam, Md Mobaidul
    Jang, Jin
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2022, 50 (03) : 1015 - 1020
  • [32] Mobility impact on compensation performance of AMOLED pixel circuit using IGZO TFTs附视频
    Congwei Liao
    Journal of Semiconductors, 2019, (02) : 33 - 38
  • [33] Level shifter circuit having dual outputs for FPD gate driver
    Yang, YS
    Kim, J
    Roh, TM
    Lee, DW
    Kwon, SK
    Park, IY
    Yu, BG
    VLSI'03: PROCEEDINGS OF THE INTERNATIONAL CONFERENCE ON VLSI, 2003, : 173 - 177
  • [34] Design and Analysis of the Gate Driver Circuit for Power Semiconductor Switches
    Kumar, Ashutosh
    Mandal, R. K.
    Raushan, Ravi
    Gauri, Pratyush
    2020 INTERNATIONAL CONFERENCE ON EMERGING FRONTIERS IN ELECTRICAL AND ELECTRONIC TECHNOLOGIES (ICEFEET 2020), 2020,
  • [35] A physical channel-potential and drain-current model for asymmetric dual-gate a-IGZO TFTs
    Minxi CAI
    Ruohe YAO
    ScienceChina(InformationSciences), 2019, 62 (06) : 180 - 182
  • [36] A physical channel-potential and drain-current model for asymmetric dual-gate a-IGZO TFTs
    Minxi Cai
    Ruohe Yao
    Science China Information Sciences, 2019, 62
  • [37] Active matrix touch sensor detecting time-constant change implemented by dual-gate IGZO TFTs
    Tai, Ya-Hsiang
    Chiu, Hao-Lin
    Chou, Lu-Sheng
    SOLID-STATE ELECTRONICS, 2012, 72 : 67 - 72
  • [38] A physical channel-potential and drain-current model for asymmetric dual-gate a-IGZO TFTs
    Cai, Minxi
    Yao, Ruohe
    SCIENCE CHINA-INFORMATION SCIENCES, 2019, 62 (06)
  • [39] Highly Reliable Gate Driver on Array Circuit Using Time-Division Driving Method Base on IGZO Thin Film Transistor
    Zhou L.-F.
    Shao X.-J.
    Wang H.-H.
    Wang B.-P.
    Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2023, 51 (12): : 3463 - 3472
  • [40] Improving the fabricated Rate and Reliability of Top Gate a-IGZO TFTs under Positive Bias Stress by Using Double-Stacked Gate Insulator Layer Design
    Huang, Bo-Shen
    Chang, Ting-Chang
    Tai, Mao-Chou
    Yen, Po-Yu
    2023 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI-TSA/VLSI-DAT, 2023,