Flip-Lock: A Flip-Flop-Based Logic Locking Technique for Thwarting ML-based and Algorithmic Structural Attacks

被引:1
作者
Darjani, Armin [1 ]
Kavand, Nima [1 ]
Kumar, Akash [2 ]
机构
[1] Tech Univ Dresden, Dresden, Germany
[2] Ruhr Univ Bochum, Bochum, Germany
来源
PROCEEDING OF THE GREAT LAKES SYMPOSIUM ON VLSI 2024, GLSVLSI 2024 | 2024年
关键词
Logic Locking; Structural attacks; ML-based attacks; Design-for-trust; Reverse engineering;
D O I
10.1145/3649476.3658753
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Machine learning (ML) and algorithmic structural attacks have highlighted the possibility of utilizing structural leakages of an obfuscated circuit to reverse engineer the locking mechanism. These structural leakages are rooted in security-agnostic synthesis tools that lead to discernible patterns within the vicinity of the locking substructures. This paper has two contributions. Firstly, we present the innovative Flip-lock, a novel approach that utilizes flip-flops along logic gates to prevent synthesis tools' structural leakages. As this is the first work that incorporates flip-flops in locking structures, our second contribution is the development of a comprehensive analysis tool designed to identify and assess potential structural leakages in the vicinity of flip-flops within circuits. We name our tool Flip-attack. We employ the Flip-attack analysis to strengthen Flip-lock's resilience against potential future attacks. Our findings demonstrate that Flip-lock possesses the capability to neutralize all existing state-of-the-art structural attacks effectively. Furthermore, by enhancing Flip-lock through the incorporation of our analysis tool, we establish a robust defense mechanism that can safeguard the circuit's security against potential future threats.
引用
收藏
页码:185 / 191
页数:7
相关论文
共 20 条
[1]   SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking [J].
Alaql, Abdulrahman ;
Rahman, Md Moshiur ;
Bhunia, Swarup .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2021, 29 (08) :1529-1542
[2]  
Alrahis L, 2022, DES AUT TEST EUROPE, P694, DOI 10.23919/DATE54114.2022.9774603
[3]   OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking [J].
Alrahis, Lilas ;
Patnaik, Satwik ;
Shafique, Muhammad ;
Sinanoglu, Ozgur .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2022, 69 (03) :1602-1606
[4]   GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking [J].
Alrahis, Lilas ;
Patnaik, Satwik ;
Khalid, Faiq ;
Hanif, Muhammad Abdullah ;
Saleh, Hani ;
Shafique, Muhammad ;
Sinanoglu, Ozgur .
PROCEEDINGS OF THE 2021 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2021), 2021, :780-785
[5]  
[Anonymous], 2022, Impedanceverif: On-chip impedance sensing for systemlevel tampering detection
[6]  
Chakraborty P, 2018, PROCEEDINGS OF THE 2018 ASIAN HARDWARE ORIENTED SECURITY AND TRUST SYMPOSIUM (ASIANHOST), P56, DOI 10.1109/AsianHOST.2018.8607163
[7]   Predictive Model Attack for Embedded FPGA Logic Locking [J].
Chowdhury, Prattay ;
Sathe, Chaitali G. ;
Schafer, Benjamin Carrion .
2022 ACM/IEEE INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN, ISLPED 2022, 2022,
[8]   SimLL: Similarity-Based Logic Locking Against Machine Learning Attacks [J].
Chowdhury, Subhajit Dutta ;
Yang, Kaixin ;
Nuzzo, Pierluigi .
2023 60TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, DAC, 2023,
[9]   ENTANGLE: An Enhanced Logic-locking Technique for Thwarting SAT and Structural Attacks [J].
Darjani, Armin ;
Kavand, Nima ;
Rai, Shubham ;
Wijtvliet, Mark ;
Kumar, Akash .
PROCEEDINGS OF THE 32ND GREAT LAKES SYMPOSIUM ON VLSI 2022, GLSVLSI 2022, 2022, :147-151
[10]  
Darjani Armin, 2023, DAC