A novel controlled shutdown scheme for DC-DC converters enabling energy recycling

被引:0
|
作者
Deka, Anup J. [1 ]
Tyagi, Shobhit [1 ]
机构
[1] Intel Technol India Pvt Ltd, Bangalore, Karnataka, India
来源
PROCEEDINGS OF THE 37TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, VLSID 2024 AND 23RD INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, ES 2024 | 2024年
关键词
Solid State Drive; voltage regulator; DC-DC converters; graceful shutdown; PMIC;
D O I
10.1109/VLSID60093.2024.00115
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
DC-DC Converters in PMICs (Power Management ICs) typically have large output capacitors to minimize droop (100s of uF) depending on the use cases i.e. transient load step and Vmin. When a rail is ramped down to 0V during shutdown, most of the energy stored in these output capacitors is dumped onto the ground. In case of catastrophic events demanding immediate shutdown like imminent power loss or depleted battery, recycling the charge stored in output capacitors of non-critical rails to input capacitor can help in keeping the critical rails up for a longer time. This allows graceful shutdown of system in many applications and especially in SSDs, provides time for data transfer from SSD storage buffer to Non-Volatile NAND flash memory mitigating risk of data loss during a Power Loss Event. A novel Si proven control scheme that enables 50% higher energy recycling than a conventional buck converter without any area penalty of additional circuit is described here.
引用
收藏
页码:649 / 654
页数:6
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