A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and <-255-dB FOMjitter

The demand for multi-band, low-power, and low-noise frequency synthesizers is growing rapidly due to increasing battery-operated Internet-of-Things (IoT) devices and high-speed communication systems. This paper proposes a low-power and dual-band sub-sampling phase-locked loop (SSPLL) with a low jitter requirement that uses a current reuse LC voltage control oscillator (LC-VCO). The proposed SSPLL can be configured at 2.4 GHz and 5 GHz frequencies by setting the frequency selection bits in the LC-VCO. The LC-VCO uses a supply-switching technique to minimize the power consumption of the design. The dual-band (2.4/5 GHz) frequencies are generated using a shared LC-tank, which saves around 46% of the LC-VCO core area. The proposed SSPLL is designed and simulated in a 65-nm industrial process node. The rigorous stability analysis and the modelling of the proposed SSPLL are performed, which shows the proposed SSPLL is stable at both 2.4 GHz and 5 GHz frequencies. To reduce the power consumption of the proposed SSPLL, the LC-VCO operates at a supply voltage of 0.9-V, while the rest of the blocks in the SSPLL work at a 1.2-V power supply. The parasitic extracted (PEX) netlist simulations of the proposed SSPLL architecture can produce 2.4 GHz and 5 GHz frequencies with a power consumption of 3.91 mW and 4.02 mW, respectively. The proposed SSPLL design achieves the rms jitter of 89.74 fs and 84.45 fs for 2.4 GHz and 5 GHz frequency modes, respectively, in the 10 kHz-100 MHz integration bandwidth. The jitter-power figure of merit (FOM) of the proposed SSPLL architecture is found to be -255.02 dB and -255.42 dB for 2.4 GHz and 5 GHz frequency operation, respectively. The total area of the layout of the proposed design is 0.253 mm(2).