Organic Ternary Logic Inverter Using Negative Transconductance Pull-Down Switching Transistor

被引：0

作者：

Kim, Somi ^{[1
]}

Jeon, Yunchae ^{[1
]}

Cho, Hong-Rae ^{[1
]}

Kim, Chang-Hyun ^{[2
]}

Yoo, Hocheon ^{[1
]}

机构：

[1] Gachon Univ, Dept Elect Engn, Seongnam 13120, South Korea

[2] Univ Ottawa, Sch Elect Engn & Comp Sci, Ottawa, ON K1N 6N5, Canada

来源：

IEEE ELECTRON DEVICE LETTERS | 2024年 / 45卷 / 04期

关键词：

Multi-valued logic; ternary logic circuit; negative transconductance; organic field effect transistor;

D O I：

10.1109/LED.2024.3368346

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study presents a novel approach to designing a ternary inverter utilizing a negative transconductance (NTC) behavior field-effect transistor (FET) with pull-down switching. The NTC FET is constructed by combining partially-deposited p-type and n-type semiconductors. The key advantages of the NTC FET, including hysteresis-free operation and a clear peak-to-valley current ratio (PVCR) of 9.6 A/A, enable the proposed ternary inverter to exhibit stable transient characteristics over a duration of 250 sec, covering three logic states. The effectiveness of the design is further supported by experimental results and simulation analysis.

引用

页码：590 / 592

页数：3

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